/*
 * Copyright (c) 2025 Core Devices LLC
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB_DMA_CONFIG_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB_DMA_CONFIG_H_

#define SF32LB_DMA_PL_POS       0U
#define SF32LB_DMA_PL_MSK       (3UL << SF32LB_DMA_PL_POS)
#define SF32LB_DMA_PL_LOW       (0UL << SF32LB_DMA_PL_POS)
#define SF32LB_DMA_PL_MEDIUM    (1UL << SF32LB_DMA_PL_POS)
#define SF32LB_DMA_PL_HIGH      (2UL << SF32LB_DMA_PL_POS)
#define SF32LB_DMA_PL_VERY_HIGH (3UL << SF32LB_DMA_PL_POS)

#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB_DMA_CONFIG_H_ */
